1. Field of the Invention
The present invention relates to a semiconductor device provided with a potential generating circuit boosting an externally applied power supply potential.
2. Description of the Background Art
Conventionally, a dynamic random access memory (DRAM) is provided with a boost circuit generating a potential higher than an externally applied power supply potential for driving a word line of a memory array.
FIG. 16 is a diagram showing an arrangement of the memory cell of the DRAM.
Referring to FIG. 16, a memory cell MC includes: an N channel MOS transistor 302 connected between a bit line BL and a storage node SN and having its gate connected to a word line; a capacitor 304 having its one end connected to storage node SN and the other end connected to a cell plate potential Vcp.
A substrate of N channel MOS transistor 302 is in most cases set at a negative back gate potential Vbb when a P type substrate is used. Cell plate potential Vcp applied to the other end of the capacitor is in most cases set at a potential half power supply potential Vcc.
Here, assume that an H (High) level is written as data to memory cell MC. Then, power supply potential Vcc is applied to bit line BL and N channel MOS transistor 302 is rendered conductive upon activation of word line WL. Power supply potential Vcc is transmitted to storage node SN.
FIG. 17 is a diagram shown in conjunction with a potential applied to N channel MOS transistor 302 when data at the H level is written to the memory cell.
Referring to FIG. 17, assume that storage node is initially set at a ground potential and then attains to power supply potential Vcc by application of power supply potential Vcc from bit line BL. In this case, N channel MOS transistor 302 has its drain D, source S, and gate G respectively connected to a bit line; storage node SN, and word line. When storage node SN attains to power supply potential Vcc, a large voltage of Vbbxe2x88x92Vcc is applied as a substrate bias voltage Vbs of N channel MOS transistor 302 because of substrate potential Vbb.
Inherently, a threshold voltage Vth of an access transistor used for the memory cell is set at a value greater than a threshold voltage of an N channel MOS transistor used for a usual peripheral circuit to reduce a subthreshold leakage current and to enhance refresh properties. As stated previously, if the source potential and substrate bias voltage Vbs increase, the threshold voltage of N channel MOS transistor 302 increases due to a substrate bias effect.
FIG. 18 is a graph showing a relationship between substrate bias voltage Vbs and threshold voltage Vth.
Referring to FIGS. 17 and 18, assume that the threshold voltage is Vt0 when substrate bias voltage Vbsr of N channel MOS transistor 302 is 0V.
When an L level is written to;storage node SN of the memory cell and the potential at storage node SN is 0V, the value of substrate bias voltage Vbs equals to substrate potential Vbb and threshold voltage Vth equals to threshold voltage Vt1 shown in FIG. 18.
Then, when data at the H level is written to the memory cell, storage node SN attains to potential Vcc, so that substrate bias voltage Vbs equals to |Vbbxe2x88x92Vcc|. Thus, threshold voltage Vth increases to attain to threshold voltage Vt2 shown in FIG. 18.
To enable transmission of power supply potential Vcc at the H level of bit line BL to storage node SN without causing any voltage drop, the potential of word line WL must be set; at a value higher than power supply potential Vcc by threshold voltage Vth.
FIG. 19 is a graph showing a relationship between a voltage written to the memory cell and a potential for activating the word line required therefor.
Referring to FIG. 19, a line G1 represents a potential transmitted to storage node SN of the memory cell. A line G2 represents a value obtained by adding the threshold voltage of the memory cell transistor to the potential of line G1. When 0V at the L level is written to the memory cell, the difference between lines G1 and G2 corresponds to threshold voltage Vt1 shown in FIG. 18. On the other hand, when power supply potential Vcc at the H level is to be written to the memory cell, line G2 becomes higher than line G1 by threshold voltage Vt2. A lower limit of the activation potential actually applied to the word line is obtained by further adding a margin to the potential of line G2 as depicted by a line G3.
The actual activation potential of the word line is set with reference to the case where the writing voltage requiring a high activation potential is power supply potential Vcc. Thus, line G3 equals to that indicating the activation potential of word line WL when power supply potential Vcc is changed.
Namely, the potential required for activation of the word line changes in accordance with the change in power supply potential Vcc and in consideration of the change in the substrate bias effect of the threshold voltage.
The activation potential of word line WL is in most cases boosted potential Vpp obtained by internal boosting.
FIG. 20 is a diagram shown in conjunction with a basic principle of a conventional boost circuit generating boosted potential Vpp.
Referring to FIG. 20, a boost circuit 310 includes: a diode 312 having its anode and cathode respectively connected to power supply potential Vcc and a node N11 for precharging node N11 to power supply potential Vcc; an oscillation circuit 316 generating a clock signal for a boosting operation; a capacitor 314 having its one end and the other end respectively connected to node N11 and an output of clock generation circuit 316; and a diode 318 having it anode connected to node N11 and cathode outputting boosted potential Vpp. When node N11 is precharged to power supply potential Vcc by diode 312 for precharging, node N11 is boosted to a value twice power supply potential Vcc from power supply potential Vcc by a clock signal generated by oscillation circuit 316 of which L and H levels respectively correspond to a ground potential and power supply potential Vcc. The boosted potential is output as boosted potential Vpp through diode 318.
It is noted that the foregoing description ignores a voltage drop in a forward direction due to diodes 312 and 318 for simplification.
FIG. 21 is a circuit diagram showing an actual arrangement of a boost circuit.
Referring to FIG. 21, a boost circuit 320 includes capacitors 321 and 322 having their one ends receiving clock signals CLK. The other end of capacitor 321 is connected to a node N12. The other end of capacitor 322 is connected to a node N13.
Boost circuit 320 further includes: an N channel MOS transistor 324 diode-connected to N12 from a node to which power supply potential Vcc is applied; an N channel MOS transistor 326 diode-connected to N13 from the node to which power supply potential Vcc is applied; and an N channel MOS transistor 328 connected between nodes N12 and N14 and having its gate connected to node N13 and its back gate supplied with substrate potential Vbb. Boosted potential Vpp is output from node N14.
Before operation, nodes N12 and N13 are precharged to power supply potential Vcc or a potential lower than power supply potential Vcc by a threshold voltage of the N channel MOS transistor. The precharge is performed by N channel MOS transistors 324 and 326 which are diode-connected.
Clock signal CLK is input, and the potential at one ends of capacitors 321 and 322 are boosted to power supply potential Vcc from 0V.
Then, nodes N12 and N13 attain to a potential twice power supply potential Vcc from power supply potential Vcc due to capacitive coupling. The potential twice power supply potential Vcc at node N12 is supplied to node N14 through N channel MOS transistor 328. At the time, boosted potential Vpp decreases by threshold voltage Vthn of N channel MOS transistor 328.
Namely, in the circuit shown in FIG. 21, the high potential at node N12 is decreased by the threshold voltage of N channel MOS transistor 328 for output.
Next, a conventional boost circuit capable of outputting higher boosted potential Vpp will be described.
FIG. 22 is a circuit diagram showing an arrangement of boost circuit 330.
Referring to FIG. 22, boost circuit 330 uses an N channel MOS transistor 334 having a triple-well structure for outputting boosted potential Vpp. N channel MOS transistor 334 has its back gate connected to a node N15.
FIG. 23 is a cross sectional view showing N channel MOS transistor 334.
Referring to FIG. 23, an N well 344 is formed in a main surface of a P substrate 342, and a P well 345 is formed in N well 344. N well 344 is connected to node N15 through an N type impurity region 346. P well 345 is connected to node N15 through a P type impurity region 350. Further, N channel MOS transistor MOS transistor 334 is formed in a main surface of P well 345. N channel MOS transistor 334 includes N type impurity regions 352 and 354 as well as a gate electrode 356. Impurity region 352 is connected to node N15, and a capacitor 332 is connected between gate electrode 356 and node NIB. Boosted potential Vpp is output from impurity region 354.
Node N15 is connected to P well 345 through impurity region 350. The potential at node N15 is transmitted to impurity region 354 through a PN junction between impurity region 354 and P well 345. Accordingly, the node at Vpp attains to a potential lower by a Pn junction voltage Vjv from a potential twice power supply potential Vcc. However, generally, since the PN junction voltage Vjv is lower than threshold voltage Vth of N channel MOS transistor 334, a higher boosted potential can be generated than in the case of the circuit shown in FIG. 21.
FIG. 24 is a circuit diagram showing an arrangement of a conventional boost circuit 360 capable of outputting still higher boosted potential.
Referring to FIG. 24, boost circuit 360 includes; a capacitor 362 having its one end supplied with clock signal CLK and the other end connected to a node N16; a level converting portion 364 having its input receiving clock signal CLK for amplifying the amplitude thereof for output; a capacitor 366 connected between an output of level converting portion 364 and a node N17; and N channel MOS transistor 368 having its gate connected to node N17 and outputting a boosted potential at node N16 as boosted potential Vpp when it is rendered conductive. N channel MOS transistor 368 has its back gate connected to a substrate potential Vbb.
FIG. 25 is a circuit diagram showing an arrangement of level converting portion 364 shown in FIG. 24.
Referring to FIG. 25, level converting portion 364 includes: an inverter 372 receiving and inverting an input signal IN; an N channel MOS transistor 374 connected between a ground node and a node N18 and having its gate receiving an input signal IN, an N channel MOS transistor 376 connected between a node N19 and the ground node and having its gate receiving an output from inverter 372; a P channel MOS transistor 378 connected between a node to which boosted potential Vpp is applied and node N18 and having its gate connected to node N19; and a P channel MOS transistor 380 connected between the node to which boosted potential Vpp is applied and node N19 and having its gate connected to node N18. An output signal OUT obtained by amplifying the amplitude of input signal IN is output from node N19.
Returning to FIG. 24, the operation of boosted circuit 360 will briefly be described. The gate potential of N channel MOS transistor 368 is boosted to a potential higher than a potential twice power supply potential Vcc by an output from level converting portion 364. Accordingly, the potential twice power supply potential Vcc at node N16 can be output as boosted potential Vpp without causing any potential drop.
FIG. 26 is a circuit diagram showing an arrangement of another boost circuit 380 which has been modified as in the case of boost circuit of FIG. 24.
Referring to FIG. 26, boost circuit 380 includes: a capacitor 382 having its one end supplied with clock signal CLK and the other end connected to a node N20; an inverter 384 receiving and inverting clock signal CLK; a capacitor 386 having its one end supplied with clock signal CLK and the other end connected to a node N21; a diode 388 precharging node N21 to power supply potential Vcc; a P channel MOS transistor 390 connected between nodes N21 and N22 and having its gate receiving an output from inverter 384; and an N channel MOS transistor 392 connected between node N22 and a ground node and having its gate receiving an output from inverter 384.
Boost circuit 380 further includes: a capacitor 394 connected between nodes N22 and N23; a diode 396 for precharging node N23 to power supply potential Vcc; and an N channel MOS transistor 398 connected between nodes N20 and N24 and having its gate connected to a node N23. Boosted potential Vpp is output from node N24.
FIG. 27 is a diagram showing waveforms in conjunction with the operation of boost circuit 380.
Referring to FIGS. 26 and 27, in the initial state, nodes N21 and N23 are precharged to power supply potential Vcc respectively by diodes 388 and 396. Then, when clock signal CLK rises from 0V to power supply potential Vcc, the potential at node N21 is boosted to a potential twice power supply potential Vcc from power supply potential Vcc. The potential is transmitted to node N22, and the potential at node N23 is boosted to a potential three times power supply potential Vcc from power supply potential Vcc by capacitive coupling of capacitor 394. More specifically, the potential at node N23 which has conventionally been set twice the power supply potential can be boosted to the potential three times power supply potential Vcc. Accordingly, the potential twice the power supply potential generated by capacitor 382 at node N20 can be transmitted by N channel MOS transistor 398 having its gate receiving the potential three times the power supply potential without causing any potential drop.
FIG. 28 is a circuit diagram showing an arrangement of a boost circuit 400 which uses a P channel MOS transistor at an output portion.
Referring to FIG. 28, boost circuit 400 includes: inverters 404 and 406 connected in series and receiving clock signal CLK; a capacitor 408 having its one end connected to an output from inverter 406 and the other end connected to a node N25; a level converting circuit 402 receiving clock signal CLK and converting the level thereof for output to node N26; and asp P channel MOS transistor 410 connected between nodes N25 and N27 and having its gate connected to a node N26.
P channel MOS transistor 410 has its back gate connected to a node N27. Boosted potential Vpp is transmitted from node N27. Boosted potential Vpp is also supplied to level converting circuit 402.
FIG. 29 is a circuit diagram showing an arrangement of level converting circuit 402.
Referring to FIG. 29, level converting circuit 402 includes: an inverter 412 receiving and inverting an input signal IN; an N channel MOS transistor 414 having its gate receiving input signal IN and connected between node N21 and a ground node; an N channel MOS transistor 416 connected between a node N29 and the ground node and having its gate receiving an output from inverter 412; a P channel MOS transistor 418 connected between a node to which boosted potential Vpp is applied and a node N28 and having its gate connected to a node N29; and a P channel MOS transistor 420 connected between the node to which boosted potential Vpp is applied and node N29 and having its gate connected to node N28.
Level converting circuit 402 further includes: a P channel MOS transistor 424 connected between the node to which boosted potential Vpp is applied and a node N30 and having its gate connected to N29; and an N channel MOS transistor 422 connected between node N30 and the ground node and having its gate connected to node N29. An output signal OUT from level converting circuit 402 is output from node N30.
Returning to FIG. 28, the operation of a boost circuit 400 will briefly be described.
Before operation, node N25 is precharged to power supply potential Vcc or a potential lower than power supply potential Vcc by the threshold voltage.
Then, a pulse is applied to clock signal CLK and the potential at node N25 is boosted to a potential twice power supply potential Vcc by capacitive coupling of capacitor 408.
At the time, a signal obtained by inverting a clock signal CLK is applied to the gate of N channel MOS transistor 410 by level converting circuit 402. The amplitude of the inverted signal has been amplified to attain to boosted potential Vpp from 0V. When the potential at node N25 attains to 2Vcc, the potential at node N26 attains to 0V. P channel MOS transistor 410 is rendered conductive for outputting the potential at node N25 without causing any potential drop. When clock signal CLK is at the L level, node N26 attains to boosted potential Vpp, and P channel MOS transistor 410 is rendered non-conductive.
FIG. 30 is a circuit diagram showing an arrangement of another exemplary boost circuit 430 which uses a P channel MOS transistor at an output portion.
Referring to FIG. 30, boost circuit 430 includes: inverters 434 and 436 connected in series and receiving clock signal CLK; a capacitor 438 having its one end supplied with an output of inverter 436 and the other end connected to a node N31; an inverter 432 receiving and inverting clock signal CLK; a capacitor 440 having its one end receiving an output of inverter 432 and the other end connected to a node N32; an N channel MOS transistor 442 diode-connected in a forward direction to a node supplied with power supply potential Vcc from node N31; an N channel MOS transistor 444 diode-connected in a forward direction to a node supplied with power supply potential Vcc from N32; and a P channel MOS transistor 446 connected between nodes N31 and N33 and having its gate connected to node N32. P channel MOS transistor 446 has its back gate connected to a node N33, from which boosted potential Vpp is output.
The operation of boost circuit 430 will briefly be described. First, before operation, node N31 is precharged to power supply potential Vcc or a potential lower than the power supply potential by the threshold voltage. When clock signal CLK changes from the L to H level, the potential at node N31 is boosted to a potential twice power supply potential Vcc by a capacitive coupling of capacitor 438.
At the time, the potential at node N32 is precharged by N channel MOS transistor 444 even if the potential is to decrease due to the capacitive coupling of capacitor 440. Thus, it is maintained at power supply potential Vcc. Namely, P channel MOS transistor 446 is rendered conductive since node N31 is twice the power supply potential and the gate is at power supply potential Vcc. Thus, the potential twice the power supply potential is transmitted to node N33 without causing any voltage drop.
On the other hand, when clock signal CLK falls from the H to L level, node N31 is precharged by N channel MOS transistor 442 and attains to power supply potential Vcc. Node N32 attains to the potential twice power supply potential Vcc due to the capacitive coupling of capacitor 440. Namely, the gate potential equals to boosted potential Vpp, so that P channel MOS transistor 446 is rendered non-conductive.
FIG. 31 is a schematic diagram shown in conjunction with a load circuit connected to the boost circuit.
Referring to FIG. 31, boosted potential Vpp output from boost circuit 310, previously described with reference to FIG. 19, is used as a power supply potential of a circuit which requires a boosting level such as a word driver 452 or a row decoder 454 of the DRAM. When the access operation of the DRAM starts, boosted potential Vpp decreases due to current consumption. If the potential is kept at a decreased level, the potential of the word line driven by word driver 452 does not sufficiently increase, or a time required for driving the word line increases. As a result, performance degradation or malfunction is caused.
If boost circuit 310 is always operated to maintain the level of boosted potential Vpp high, however, the DRAM generally consumes a greater amount of current. Then, measures are taken to reduce the amount of current consumed.
FIG. 32 is a block diagram showing an arrangement of generating boosted potential Vpp employed in the conventional case.
Referring to FIG. 32, a detector circuit 462 for monitoring boosted potential Vpp is arranged. Detector circuit 462 operates a ring oscillator 464 by an activation signal /OE to generate a clock signal when boosted potential Vpp decreases. Responsively, boost circuit 466 boosts boosted potential Vpp by a pumping operation. When boosted potential attains at least to a set potential, detector circuit 462 inactivates ring oscillator 464 to stop clock signal CLK and the pumping operation of boost circuit 466. Further, when a row-related command which causes semiconductor memory device to receive boosted potential Vpp and consume a large amount of current is input, for example, boost circuit 468 activated in synchronization with input control signal /RAS may be arranged.
FIG. 33 is a circuit diagram showing a first example of detector circuit 462 shown in FIG. 32.
Referring to FIG. 33, a detector circuit 462a of the first example includes: an N channel MOS transistor 472 connected between a node N34 supplied with boosted potential Vpp and a node N35 and having its gate connected to power supply potential Vcc; and a resistor 474 connected between node N35 and the ground node. Control signal /OE of an activation signal is output from node N35.
A transistor having a large threshold voltage is for example used for a memory array portion of N channel MOS transistor 472. In the case of detector circuit 462a, control signal /OE is controlled such that boosted potential Vpp equals to Vcc+Vth (memo). It is noted that threshold voltage Vth (memo) is a threshold voltage of N channel MOS transistor 452.
FIG. 34 is a circuit diagram showing a second example of detector circuit 462.
Referring to FIG. 34, a detector circuit 462b includes: a P channel MOS transistor 476 connected between node N34 supplied with boosted potential Vpp and node N36 and having its gate connected to node N36; a P channel MOS transistor 478 connected between nodes N36 and N35 and having its gate connected to power supply potential Vcc; and a resistor 480 connected between node N35 and a ground node. A control signal /OE is output from node N35.
In the case of detector circuit 462b, control signal /OE is controlled such that boosted potential Vpp equals to Vcc+2Vthp. It is noted that Vthp is a threshold voltage of P channel MOS transistors 476 and 478.
More specifically, when boosted potential Vpp falls below a set value, P channel MOS transistors 476 and 478 are rendered conductive and control signal /OE attains to the H level. When boosted potential Vpp attains at least to the set value, P channel MOS transistors 456 and 458 are rendered non-conductive and node N35 attains to the L level because of resistor 460, so that control signal /OE also attains to the L level.
Recently, the devices with the DRAMs are required to consume less power. Thus, in the DRAMs, externally applied power supply potential Vcc is becoming lower. Here, a DRAM operating with a low power supply voltage will be considered.
FIG. 35 is a graph showing a relationship between a power supply potential and a boosted potential.
Referring to FIG. 35, Vpp equals to Vcc at any point on a line G10, and Vpp equals to 2Vcc at any point on a line G14.
In the conventional boost circuit which has been described above, even an ideal circuit can generate Vpp as low as twice power supply potential Vcc. Namely, the level of boosted potential Vpp has a slope which is twice as sharp as the change in power supply potential Vcc. To write power supply potential Vcc to the memory cell, the activation potential of the word line must be a potential (a line G11) higher by the threshold voltage of the memory cell. In addition, an operation margin, control margin and the like are required, so that the potential of a line G13 is necessary for actually driving the word line of the memory cell. Namely, the boost circuit must output a potential higher than that of line G13.
However, even in the ideal boost circuit, boosted potential Vpp, i.e., an output potential, has a slope twice as sharp as that of power supply potential Vcc. Thus, a decrease in power supply potential Vcc results in a sharp decrease in the output potential. Then, a required potential (line G13) and the supplied potential (line G14) become equal at a point A. Therefore, a potential required for driving the word line cannot be generated on the lower voltage side of point A.
To achieve a circuit capable of ideally outputting a potential twice as power supply potential Vcc, conventionally, a triple-well process as shown in FIGS. 21 and 22 is used, the number of circuit elements is increased as shown FIGS. 23 and 25 to increase the gate potential, or the P channel MOS transistor is used at the output portion to prevent the decrease by the threshold voltage as shown in FIGS. 26 and 28. However, any of these measures suffer from the problems that the process becomes complicated, the number of circuit elements increases, or the element size of the P channel MOS transistor with less mobility increases, thereby resulting in increase in the layout area.
An object of the present invention is to provide a semiconductor device provided with a boost circuit which is capable of generating a suitable boosted potential Vpp even when an externally applied power supply voltage is low and which is advantageous in terms of the number of circuit, layout area, current consumption and process.
In short, the present invention is a semiconductor device provided with a voltage detecting portion, a clock signal generation circuit, and a boosting portion.
The voltage detecting portion detects a potential at a first node supplied with a boosted potential. The clock signal generation circuit generates an source clock signal in accordance with an output from the detection circuit. The boosting portion boosts an external power supply potential in accordance with the source clock signal for applying it to the first node.
The boosting portion includes: a precharge circuit precharging a second node to a prescribed potential; a boost circuit boosting the potential at the second node in accordance with the source clock signal; a first field effect transistor of a first conductivity type connected between the first and second nodes; a first driving circuit driving the gate potential of the first field effect transistor in accordance with the source clock signal; a second field effect transistor of a second conductivity type connected between the first and second nodes; and a second driving circuit driving the gate potential of the second field effect transistor in accordance with the source clock signal.
Therefore, a main advantage of the present invention is that a driver formed by the P channel MOS transistor is also used together with a driver formed by the N channel MOS transistor, so that a high boosted potential can be supplied while avoiding a problem of voltage drop by the threshold voltage of the driver, which is caused in the case of the N channel MOS transistor.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.